A conventional flat no-lead package has no pins extending beyond edges of the package. Thus, it is beneficial for the flat no-lead package to have a size smaller than that of a leaded chip carrier package including a plurality of pins extending outwardly. However, exposed surfaces of the pins along the edges of the package may not provide sufficient wettable flanks to provide reliable electrical and mechanical connections to an external component, such as a printed circuit board (PCB) during a subsequent reflow soldering process.
Referring to FIG. 1, in order to improve the connection between the pins of the flat no-lead package and the external component, U.S. Patent Application Publication No. 2016/0148877 A1 discloses a method for manufacturing an integrated circuit (IC) device in a quad flat no-lead (QFN) package and an IC device in a QFN package made from the same. The method includes encapsulating a lead frame formed with a rib connecting a plurality of pins 12 and an IC chip mounted on the leadframe, cutting a step cut into the encapsulated leadframe to form a groove 13 using a first saw width without separating a bonded IC package from the rib, forming an electroplated coating 14 on the exposed pins 12, and cutting the bonded IC package free from the rib using a second saw width less than the first saw width.
Formation of the step cut may increase the wettable flanks to enhance electrical and mechanical connections of the IC package to the external component during the reflow soldering process but involves the two cutting steps that are carried out posterior to the encapsulating operation of the lead frame and the IC chip. The manufacturing cost is relatively high and the manufacturing process is relatively complicated.